Strain-induced improvement of electron or hole mobility is a very attractive way of enhancing the speed performance of integrated circuits in addition to device scaling. This paper reviews several promising substrate technologies for the exploitation of strain-induced effects. Strained silicon substrates incorporating layer structures such as strained-Si on a relaxed SiGe buffer layer, strained-Si-on-insulator, and strained-Si/SiGe-on-insulator, are examined. Technical challenges for these substrate technologies are investigated, and their relative merits are compared.

Keywords: Strain, transistor, CMOS, substrate